The present invention relates generally to methods for bump and trace layout for an integrated circuit die. More specifically, but without limitation thereto, the present invention relates to a bump and trace layout for increasing the ratio of signal-to-power connections for a flip chip integrated circuit.
In flip chip packaging technology, the I/O pads, also referred to as xe2x80x9cbumpsxe2x80x9d, make electrical contact with pads on a package when the die is turned contact side down, or flipped, and attached to the top surface of the package. A goal of flip chip packaging is to increase the number of I/O devices that can be accommodated on a flip chip using the same minimum I/O pad spacing, or bump pitch. A need therefore exists for a way to accommodate more I/O pads with the same minimum bump pitch.
The present invention advantageously addresses the needs above as well as other needs by providing a six-to-one signal-to-power ratio bump and trace layout for a flip chip.
In one embodiment, the invention may be characterized as a method that includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.
In another embodiment, the invention may be characterized as an integrated circuit die that includes a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.